The present invention relates to a semiconductor device and a method of manufacturing the same, which are suited for use in, for example, a semiconductor device having an STI-type element isolation region and MISFET and a method of manufacturing the device.
The STI type element isolation region can be formed by burying an insulating film in a trench formed in a semiconductor substrate. An MISFET and the like are then formed in an active region of the semiconductor substrate surrounded by the element isolation region.
Japanese Unexamined Patent Application Publication No. 2007-103492 (Patent Document 1) describes a technology of introducing, in forming an n type SOI transistor in an element region surrounded by a LOCOS layer, a parasitic channel preventing boron in an end portion of a channel region and introducing, as a diffusion reducing atom, fluorine or nitrogen in the end portion of the channel region.
Japanese Unexamined Patent Application Publication No. 2003-133549 (Patent Document 2) describes a technology of relaxing an electric field between a gate electrode and an end portion of a drain to suppress generation of a leakage current.
Japanese Unexamined Patent Application Publication No. 2008-218852 (Patent Document 3) describes a technology of carrying out channel doping with an n type impurity and also fluorine implantation.
Japanese Unexamined Patent Application Publication No. Hei 11(1999)-297812 (Patent Document 4) describes a technology relating to a semiconductor device using STI.
Japanese Unexamined Patent Application Publication No. 2004-207564 (Patent Document 5) describes a technology relating to a semiconductor device using STI.
Non-patent Documents 1 and 2 describe a technology relating to NBTI.